This invention relates to a package having electronic devices such as integrated circuit chips, and in particular to a ball grid array package with reduced weight and low manufacturing cost and a method of fabricating the same.
In early generations, integrated circuit chips were packaged in a metal or a ceramic. A method for forming a semiconductor package by a metal or a ceramic has an excellent thermal properties. However, it has shortcomings such as high manufacturing cost and time consuming manufacturing techniques. To solve such shortcomings, there are proposed many packages the most notable one of which is a plastic molded package. Particularly, a plastic molded ball grid array package obviates a difficulty in surface mounting prior art fine pitch plastic packages. The plastic molded ball grid array packages also eliminate the need to route packages leads to the outer edges of the integrated circuit package. The plastic molded ball grid array packages also allow for smaller package and very close spacing of packages mounted to the same printed circuit board. Finally, ball grid array packages provide shorter interconnection lengths which results in improved electrical performance. The advantages described above, along with the low cost of ball grid array packaging, make ball grid array packages an ideal packaging format for many integrated circuit applications.
FIG. 1 shows a cross-sectional view of a prior art ball grid array package. The ball grid array package shown in FIG. 1 includes an interconnection substrate 1 with integrated circuit pattern and an integrated circuit chip 2 attached to the substrate 1 by adhesive preform 3 and having a plurality of bond pads 2a on the upper surface thereof. The circuit pattern of the substrate 1 and the bond pad 2a on the integrated circuit chip 2 are also connected to each other. Also, to protect the surface of the integrated circuit chip 2 from an outer circumstance, a wire bonding portion of the substrate 1 and the integrated circuit chip 2 are encapsulated by an epoxy resin 5. On the lower surface of the substrate 1 are attached a plurality of solder balls 6 for making electrical connection with power supply terminals formed on a mother board(not shown).
The ball grid array package shown in FIG. 1 lowers the reliability of the integrated circuit chip and still more has relatively bad heat dissipation characteristics which incur a breakdown of the integrated circuit chip. So as to dissipate the heat generated from such integrated circuit chip into the exterior of the package, there is a problem in that still more power is consumed. Also, the overall thickness of such package is very thick.
Recently, to improve the heat dissipation characteristics of the ball grid array package, a super ball grid array package having a heat sink for dissipating the heat generated therefrom has been developed.
FIG. 2 is a cross-sectional view showing the super ball grid array package having a heat sink. Referring to FIG. 2, the super ball grid array package includes an interconnection substrate 11 comprised of a conductive trace layer 22 and an insulating layer 23, and a copper layer 19 on one surface of which is attached to the insulating layer 23 of the interconnection substrate 11 by means of an adhesive preform 18. On the respective central portions of the interconnection substrate 11 and the copper layer 19 are formed an opening so that the opening forms a well region 14 through the interconnection substrate 11 and the copper layer 19. On a surface of the copper layer 19 is formed a heat sink 20 for improving the heat dissipation characteristics of the package via the adhesive layer 18a. In this regard, the heat sink 20 is thick such that it can resist a stress generated during an attachment of the integrated circuit chip to the heat sink 20, a wire bonding, and an encapsulation, which are carried out in a condition where the heat sink 20 is attached to the copper layer 19. In the well region 14, the integrated circuit chip 12 having a plurality of bond pads 12a on the surface thereof is disposed and the integrated circuit chip 12 is attached to the heat sink 20 through the adhesive preform 18b. The bond pads 12a are electrically connected to a conductive trace layer 23 via bond wires 15. Further, a wire-bonded portion of the substrate 11 and the integrated circuit chip 12 is encapsulated via insulating encapsulant material and on the surface of the substrate 11 is attached a plurality of solder balls 17 for making electrical connection of the package with a mother board(not shown).
The super ball grid array package shown in FIG. 2 has excellent heat dissipation characteristics, compared with the package shown in FIG. 1. However, since the super ball grid array package of FIG. 2 has the heavy weight, there is a problem in that the super ball grid array package can not be applied to the notebook, the pocket computer, the cellular phone, etc., in which the light weight is required. Since the expensive two or more copper layers are stacked, there is a drawback in which the cost is expensive and the thickness of the package is still thick.
Accordingly, to solve the above problems, one object of this invention is to provide a packaged integrated circuit device having an excellent heat dissipation capability, a low weight, a thinner thickness and a low manufacturing cost.
Another object of this invention is to provide a method of manufacturing the same capable of reducing the manufacturing time, an apparatus investment cost and a manufacturing cost.